Analog Bits has demo-ed its low picojoule-per-bit SERDES macro on TSMC’s 12nm process geometry. Implementations of this same multi-protocol SERDES architecture are available on a variety of TSMC process nodes and support speeds of up to 25Gb/s. The combination of high performance and low power make this suitable for short reach, chip-to-chip applications while support ...
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from Electronics Weekly https://www.electronicsweekly.com/news/business/538950-2018-10/
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