Cadence Design Systems has introduced design verification IP for three standard interfaces. These are CoaXPress for high-speed imaging, HyperRAM high-speed memory and the JEDEC Universal Flash Storage (UFS) 3.0 specification. The three tool sets will be used for IP and system-on-chip (SoC) design verification specifically for automotive devices. The UFS 3.0 specification doubles the throughput ...
This story continues at CDNLive: Cadence speeds verification of fast interfaces
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from Electronics Weekly https://www.electronicsweekly.com/market-sectors/automotive-electronics/cdnlive-cadence-speeds-verification-fast-interfaces-2018-05/
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