Designers can used the integrated development environment (IDE) to quickly go from C++ to FPGA using the HLS and Achronix’s ACE design tools. The combination can reduce the development effort for 5G wireless and other design applications that require high performance FPGA technology in SoCs, configured using a proven C‑based design flow. Ellie Burns, director of marketing, Calypto Systems division, ...
This story continues at Partners bridge HLS and FPGA technology
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from Electronics Weekly https://www.electronicsweekly.com/news/products/fpga-pld/partners-bridge-hls-fpga-technology-2018-08/
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