Imec and Pisa University have performed the first material-device-circuit level co-optimization of FETs based on 2D materials for high-performance logic applications scaled beyond the 10nm technology node. Imec also presented novel designs that would allow using mono-layer 2D materials to enable Moore’s law even below 5nm gate length. 2D materials, a family of materials that ...
This story continues at Imec enables 5nm 2D FETs
Or just read more coverage at Electronics Weekly
from Electronics Weekly https://www.electronicsweekly.com/news/business/imec-enables-5nm-2d-fets-2017-07/
No comments:
Post a Comment